1. Field of the Invention
The subject reconfigurable expert rule computing, or processing, system is generally directed to a processing system for use in artificial intelligence applications. More specifically, the subject reconfigurable expert rule processing system is directed to a highly flexible system for substantially real-time processing of data in rule based expert system applications. The emerging technological field of reconfigurable computing is requiring innovative methodologies. The subject reconfigurable expert rule processing system generally addresses this need.
With their inherent capacity to perform extremely complex operations, rule based expert systems find application in numerous control systems. They find application, for instance, in automated game control, in automated spacecraft command and control, and the like. The complexity of those control systems are such that a great number of inference rules are necessarily processed in carrying out the required control functions. Given the Von Neuman architecture invariably employed in the host processors of typical control systems, the number of inference rules to be processed yields a sufficiently great computational load to often render real time processing thereof impracticable. While real time processing may be realized with the benefit of a massive computing capability, such would be in most applications prohibitively costly, not only in terms of monetary expenses, but also in terms of electrical and mechanical resources consumed. Hence, a significant need is present for a rule based expert processing system that is realizable within the cost and operational constraints typically found in various control system applications.
Computational efficiency may be enhanced, often by orders of magnitude, through hardware implementation of combinational logic in corresponding circuits of interconnected logic gates. Indeed, it has long been a known practice in the prior art to implement logic circuits in such hardwired devices as dedicated controllers, switching circuits, and state machines. The practice of implementing logic in hardware led to the emergence of the relatively costly, yet widely accepted, practice of utilizing application specific integrated circuits (ASIC) for certain applications.
Over the past two decades, there has also emerged programmable logic devices on which the desired circuit configuration may be `burned` in by a user. Advanced forms of such programmable logic devices afford the option of erasing the `burned` in configuration, via either ultraviolet or electrical means. Like ASICs and other dedicated hardware devices, however, such programmable logic devices--even erasable ones--offer very little flexibility to the user. Where reconfiguration of the implemented circuit becomes necessary, the user must take significant reconfiguration measures that invariably require human intervention, else replace the given device altogether with one hardwired with the desired configuration.
In more recent years, dynamically programmable logic devices have emerged wherein automatic reconfiguration may be effected by passing appropriate control signals thereto. Latest generations of the field programmable gate array (FPGA) produced by Xilinx Corporation of San Jose, Calif. and the complex programmable logic device (CPLD) produced by Altera Corporation of San Jose, Calif., for instance, provide an on-board memory portion to which a configuration code may be provided. Configuration is then automatically effected by the device in accordance with that code. In the emerging field of reconfigurable computing, plug-in peripheral boards are now commercially available for personal computers that provide reconfiguration co-processing. These boards, commercially available from such companies as Virtual Computer Corporation of Reseda, Calif., and Giga Operations Corporation of Berkeley, Calif., interface with a personal computer memory bus to provide convenient memory-mapped I/O. Such boards support the subject reconfigurable expert rule processing system. Attempts have been made in the prior art to optimize the computational efficiency in systems requiring expert rule processing. These attempts have ranged from delineating a processor in a given system to serve exclusively as an inference engine to implementing select portions of the required rule processing functions in dedicated, hardwired circuitry. Such attempts have yielded varying degrees of success in accelerating the required rule processing. In control systems of even modest practicality, however, efficient processing is necessary for both rules--conditional commands or actions inferentially generated responsive to particular input signal components, and scripts--procedural command or instruction sequences to be carried out in time or procedure-based manner. Prior art approaches fail to provide a comprehensive mechanism by which efficient, coordinated processing of both rules and scripts may be realized. Furthermore, prior art approaches fail to provide such a comprehensive mechanism which is sufficiently reconfigurable to significantly enhance the performance and cost effectiveness of the resulting control system.
2. Prior Art
Expert rule processing systems are known, as are devices containing hardwired implementations of combinational logic circuits and dynamically programmable devices for performing such implementation. The best prior art references known to Applicant include U.S. Pat. Nos. 5,487,134; 5,077,677; 5,481,649; 5,072,442; 5,561,738; 5,737,235; 4,910,669; 4,551,814; 5,717,928; 5,379,387; 5,499,192; 5,574,655; 5,077,656; 5,615,309; 4,901,229; 5,673,198; 5,140,526; 5,365,514; 5,259,066; 5,487,134; 5,638,493; and, 5,428,525. There is no system heretofore known, however, which comprehensively provides in readily reconfigurable manner efficient processing of both rules and scripts in system applications employing rule based expert system architectures.